Field Programmable Gate Arrays are two-dimensional arrays of:

• Logic Blocks
  Programmable Logic Devices (PLD) which, unlike a logic gate which has a fixed function, has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed (i. e. reconfigured).
• Connections
  Flip-flops with a electrically programmable interconnections between the Logic Blocks. These consist of electrically programmable switches which is why FPGA differs from Custom ICs, as Custom IC is programmed using integrated circuit fabrication technology to form metal interconnections between logic blocks. FPGAs are programmable "in the field".

A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function, hence the name "field-programmable".

A Logic Block can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different combinations of combinational and sequential logic functions.

Logic Blocks are implemented using mutliple level low fanin gates, which gives it a more compact design compared to an implementation with two-level AND-OR logic.

Configuration
FPGA provides its user a way to configure:

• The intersection between the logic blocks and
• The function of each logic block.

Logic blocks of an FPGA can be implemented by any of the following:

• Transistor pairs
• combinational gates like basic NAND gates or XOR gates
• n-input Lookup tables
• Multiplexers
• Wide fanin And-OR structure.

Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via electrically programmable switches. Density of logic block used in an FPGA depends on length and number of wire segments used for routing. Number of segments used for interconnection typically is a tradeoff between density of logic blocks used and amount of area used up for routing.

The ability to reconfigure functionality to be implemented on a chip gives a unique advantage to designer who designs his system on an FPGA It reduces the time to market and significantly reduces the cost of production.