The Cache is a special high-speed, low volume memory that is in close proximity to the processing hardware that it is reserved for. When data is found in the cache, it’s called a cache hit. When data is not found in the cache, it is called a cache miss, and the data needs to be accessed in slower memory. The efficiency of a cache algorithms is judged by its hit/miss rate.

Embedded architectures include both Data Caches, and Instruction Caches.

Different cache levels exist:

• L1, or primary cache, is a small, high-speed cache incorporated right onto the processor’s chip. The L1 cache typically ranges in size from 8KB to 64KB and uses the high-speed SRAM (static RAM) instead of the slower and cheaper DRAM (dynamic RAM) used for main memory. Using memory cache to hold memory values, or the most recently used data and instructions (called a unified or integrated cache), means the processor can retrieve the data from the cache instead of the system’s main memory, which is much slower than the cache memory. The Intel Celeron processor uses two separate 16KB L1 caches, one for the instructions and one for the data.
• L2, or secondary cache, is memory between the RAM and the CPU (but not on the CPU chip itself) and is bigger than the primary cache (typically 64KB to 2MB). L2 ATC (Advanced Transfer Cache) uses micro-architectural im provements, which provide a higher data bandwidth interface between the L2 cache and the processor core, and is completely scaleable with the processor core frequency. The L2 cache is also a unified, non-blocking cache, which improves performance over cache-on-motherboard solutions through a dedicated 64-bit cache bus.
• L3 cache Since more manufacturers are beginning to include L2 cache into their architectures, L3 cache is slowly replacing the L2 cache function—the extra cache built into the motherboards between the CPU and the main memory (old L2 cache definition) is now being called the L3 cache.

The use of caches, while increasing overall performance, also significantly reduces testability and timing predictability of the embedded system. For this reason, the caches may be switched off for some critical applications.